ngtim 发表于 2010-6-28 00:41:09

并串转化指错,谢谢

本帖最后由 fpgaw 于 2010-7-11 11:48 编辑

module ptos(clk,ri,gi,bi,ro,go,bo);
output ro,go,bo;
input ri,gi,bi;
input clk;
reg ro,go,bo;
reg mem1,mem2,mem3;
reg i,k;
always @(negedge clk)
begin
if(i==7)
begin
i<=0;
k<=1;
end
else
begin
i<=i+1;
i<=0;
end
end
always @(posedge k)
begin
mem1<=ri;
mem2<=gi;
mem3<=bi;
end

always @(posedge clk)
begin
ro<=mem1;
go<=mem2;
bo<=mem3;
for(i=0;i<=6;i=i+1)
begin
mem1<=mem1;
mem2<=mem2;
mem3<=mem3;
end
end
endmodule
错误是多驱动mem,但是我改不出来的,谢谢各位高手

ATA 发表于 2010-6-28 02:22:27

不能在 多个ALEAYS中给同一个寄存器赋值
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