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ngtim 发表于 2010-6-28 00:19:55

用fpga控制步进电机如何设计

用fpga控制步进电机如何设计

哪位仁兄,提供一些源程序,部分也好.或能给点资料,指导指导

longt 发表于 2010-6-28 01:26:57

任意关于此方面的源程序或其他资料,提示 
都不甚感谢

HDL 发表于 2010-6-28 01:57:26

我也想要啊,不过我知道有本书上有.明天去借过来.嘿嘿^

interig 发表于 2010-6-28 03:50:19

我也想要啊, 
 

zhang18jun@163.com

longtime 发表于 2010-6-28 04:23:40

这个用有限状态机能实现吧？

VVIC 发表于 2010-6-28 05:33:57

你搜索下关于 PWM方面的资料吧

CHANG 发表于 2010-6-28 07:19:48

建议到图书馆找几本书看看，很多实例教程都有这方面的例子
http://bbs.vibesic.com/images/smilies/default/lol.gif

CHAN 发表于 2010-6-28 08:59:40

是用有限状态机,我做过的 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 
设计三相磁阻式转子步进电机控制器 
产生对A/B/C三相绕组的控制信号 
在控制信号控制下分别完成三相双三拍正转和三相六拍反转 
做出状态跳变图（通电为１，不通电为０ 
 
输入信号：rst_.复位信号，低电平有效 
                   clk，时钟信号 
　　　　　　mode,控制信号，１三相双三拍正转，０三　 
　　　　　　　相六拍反转 
输出信号：outa，ａ绕组驱动信号 
　　　　　　outb，ｂ绕组驱动信号 
                   outc，ｃ绕组驱动信号 
 
 
代码： 
module step_engineer(clk,rst_,mode,outa,outb,outc); 
input clk,rst_,mode; 
output outa,outb,outc; 
reg outa,outb,outc; 
reg state,next_state; 
parameter IDLE=3'b000, A=3'b100, B=3'b010, C=3'b001, AB=3'b110, BC=3'b011, CA=3'b101; 
always@(posedge clk or negedge rst_) 
if(!rst_) 
  state<=IDLE; 
else 
  state<=next_state; 
always@(state or rst_ or mode) 
if(!rst_) 
next_state=IDEL; 
else if(mode) 
case(state) 
  IDLE: next_state=AB; 
  AB: next_state=BC; 
  BC: next_state=CA; 
  CA: next_state=AB; 
  default: next_state=IDLE; 
endcase 
else if(!mode) 
case(state) 
  IDLE: next_state=A; 
  A: next_state=CA; 
  CA: next_state=C; 
  C: next_state=BC; 
  BC: next_state=B; 
  B: next_state=AB; 
  AB: next_state=A; 
  default: next_state=IDLE; 
endcase 
 
else if(!mode) 
case(state) 
  IDLE: next_state=A; 
  A: next_state=CA; 
  CA: next_state=C; 
  C: next_state=BC; 
  BC: next_state=B; 
  B: next_state=AB; 
  AB: next_state=A; 
  default: next_state=IDLE; 
endcase 
 
else if(!mode) 
case(state) 
  IDLE: next_state=A; 
  A: next_state=CA; 
  CA: next_state=C; 
  C: next_state=BC; 
  BC: next_state=B; 
  B: next_state=AB; 
  AB: next_state=A; 
  default: next_state=IDLE; 
endcase 
 
else if(!mode) 
case(state) 
  IDLE: next_state=A; 
  A: next_state=CA; 
  CA: next_state=C; 
  C: next_state=BC; 
  BC: next_state=B; 
  B: next_state=AB; 
  AB: next_state=A; 
  default: next_state=IDLE; 
endcase 
 
else if(!mode) 
case(state) 
  IDLE: next_state=A; 
  A: next_state=CA; 
  CA: next_state=C; 
  C: next_state=BC; 
  BC: next_state=B; 
  B: next_state=AB; 
  AB: next_state=A; 
  default: next_state=IDLE; 
endcase 
 
else if(!mode) 
case(state) 
  IDLE: next_state=A; 
  A: next_state=CA; 
  CA: next_state=C; 
  C: next_state=BC; 
  BC: next_state=B; 
  B: next_state=AB; 
  AB: next_state=A; 
  default: next_state=IDLE; 
endcase 
 
else if(!mode) 
case(state) 
  IDLE: next_state=A; 
  A: next_state=CA; 
  CA: next_state=C; 
  C: next_state=BC; 
  BC: next_state=B; 
  B: next_state=AB; 
  AB: next_state=A; 
  default: next_state=IDLE; 
endcase 
 
else if(!mode) 
case(state) 
  IDLE: next_state=A; 
  A: next_state=CA; 
  CA: next_state=C; 
  C: next_state=BC; 
  BC: next_state=B; 
  B: next_state=AB; 
  AB: next_state=A; 
  default: next_state=IDLE; 
endcase 
 
else if(!mode) 
case(state) 
  IDLE: next_state=A; 
  A: next_state=CA; 
  CA: next_state=C; 
  C: next_state=BC; 
  BC: next_state=B; 
  B: next_state=AB; 
  AB: next_state=A; 
  default: next_state=IDLE; 
endcase 
 
else if(!mode) 
case(state) 
  IDLE: next_state=A; 
  A: next_state=CA; 
  CA: next_state=C; 
  C: next_state=BC; 
  BC: next_state=B; 
  B: next_state=AB; 
  AB: next_state=A; 
  default: next_state=IDLE; 
endcase 
 
else if(!mode) 
case(state) 
  IDLE: next_state=A; 
  A: next_state=CA; 
  CA: next_state=C; 
  C: next_state=BC; 
  BC: next_state=B; 
  B: next_state=AB; 
  AB: next_state=A; 
  default: next_state=IDLE; 
endcase 
 
else if(!mode) 
case(state) 
  IDLE: next_state=A; 
  A: next_state=CA; 
  CA: next_state=C; 
  C: next_state=BC; 
  BC: next_state=B; 
  B: next_state=AB; 
  AB: next_state=A; 
  default: next_state=IDLE; 
endcase

CCIE 发表于 2010-6-28 10:34:15

always@(posedge clk or negedge rst_) 
if(!rst_) 
{outa,outb,outc}<=3'd0; 
else 
{outa,outb,outc}<=state; 
endmodule

ICE 发表于 2010-6-28 11:10:33

我这里好像有个pwm的fpga实验图，你们看看。

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用fpga控制步进电机如何设计