求教verilog 问题
AD7864转换器的控制模块设计程序如下：module ads7864_control(reset,clk,BUSY,ad_data,wraddress,wrdata,wren,WR,RD,CS);
input reset,clk,BUSY;
inout ad_data;
output wraddress;
output wrdata;
output wren,WR,RD,CS;
reg cnt0,cnt1,cnt2;
reg wraddress;
reg wrdata;
reg wren,WR,RD,CS;
reg state;
reg ad_buffer;
reg ad_data;
parameter ad_init=3'b000,ad_sample_hold=3'b001,ad_convert=3'b010,ad_cyclemode=3'b011,ad_read=3'b100,ad_finish=3'b101;
always@(posedge clk)
if(!reset)
begin
ad_data<=1;
ad_data<=1;
ad_data<=1;
ad_data<=1'bz;
ad_data<=1'bz;
ad_data<=1'bz;
RD<=1;
CS<=1;
wren<=0;
cnt0<=0;
cnt1<=0;
cnt2<=0;
WR<=1;
state<=ad_init;
end
else
begin
case(state)
ad_init:
begin
ad_data<=1;
ad_data<=1;
ad_data<=1;
ad_data<=1'bz;
ad_data<=1'bz;
ad_data<=1'bz;
RD<=1;
CS<=1;
wren<=0;
cnt0<=0;
cnt1<=0;
cnt2<=0;
WR<=1;
state<=ad_sample_hold;
end
ad_sample_hold:
begin
if(cnt0<4)
begin
ad_data<=1;
ad_data<=1;
ad_data<=1;
cnt0<=cnt0+1'b1;
end
else if(cnt0<7)
begin
ad_data<=0;
ad_data<=0;
ad_data<=0;
cnt0<=cnt0+1'b1;
end
else
begin
ad_data<=1;
ad_data<=1;
ad_data<=1;
cnt0<=0;
CS<=1;
WR<=0;
state<=ad_convert;
end
end
ad_convert:
begin
if(cnt0<67)
begin
cnt0<=cnt0+1'b1;
state<=ad_convert;
end
else
begin
cnt0<=0;
state<=ad_cyclemode;
end
ad_cyclemode:
begin
WR<=1;
ad_data<=1;
ad_data<=1;
ad_data<=0;
#2WR<=0;
CS<=0;
state<=ad_read;
end
ad_read:
begin
CS<=0;
cnt1<=cnt0;
if(cnt1<3)
begin
RD<=1;
cnt1<=cnt1+1'b1;
end
else if(cnt1<6)
begin
RD<=0;
cnt1<=cnt1+1'b1;
ad_buffer<=ad_data;
end
else if(cnt1<9)
begin
RD<=1;
cnt1<=cnt1+1'b1;
end
else if(cnt1<12)
begin
RD<=0;
cnt1<=cnt1+1'b1;
ad_buffer<=ad_data;
if(ad_buffer==1)
begin
wraddress<=ad_buffer;
wrdata<={1'b0,1'b0,1'b0,1'b0,ad_buffer};
wren<=1;
cnt2<=cnt2+1'b1;
end
else
begin
wren<=0;
cnt2<=0;
end
if(cnt2<6)
begin
state<= ad_read;
end
else
begin
cnt2<=0;
state<=ad_finish;
end
end
end
ad_finish:
begin
ad_data<=1;
ad_data<=1;
ad_data<=1;
ad_data<=1'bz;
ad_data<=1'bz;
ad_data<=1'bz;
WR<=1;
RD<=1;
CS<=1;
wren<=0;
cnt0<=0;
cnt1<=0;
cnt2<=0;
state<=ad_init;
end
default:
begin
ad_data<=1;
ad_data<=1;
ad_data<=1;
ad_data<=1'bz;
ad_data<=1'bz;
ad_data<=1'bz;
WR<=1;
RD<=1;
CS<=1;
wren<=0;
cnt0<=0;
cnt1<=0;
cnt2<=0;
state<=ad_init;
end
endcase
end
endmodule
编译后出现错误提示如下：是什么问题？
Error (10170): Verilog HDL syntax error at ads7864_control.v(96) near text ":";expecting "<=", or "="
Error (10170): Verilog HDL syntax error at ads7864_control.v(107) near text ":";expecting "<=", or "="
Error (10170): Verilog HDL syntax error at ads7864_control.v(156) near text ":";expecting "<=", or "="
Error (10170): Verilog HDL syntax error at ads7864_control.v(174) near text "default";expecting "@", or "end", or an identifier ("default" is a reserved keyword ), or a system task, or "{", or a sequential statement
Error (10170): Verilog HDL syntax error at ads7864_control.v(191) near text "endcase";expecting "@", or "end", or an identifier ("endcase" is a reserved keyword ), or a system task, or "{", or a sequential statement
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