菜鸟求助VHDL语段解释，谢谢~
有如下的程序段，搞不清楚几个信号最后的关系是什么，求高手解答。为了表达清楚把整段程序贴上了，但问题其实很简短~entity bt656gen is
port(
clk : inSTD_LOGIC;
reset : inSTD_LOGIC;
sd_din : inSTD_LOGIC_VECTOR(7 downto 0);
syn_h : out STD_LOGIC;
syn_v : out STD_LOGIC;
syn_f : out STD_LOGIC;
regenh : out STD_LOGIC;
regenf : out STD_LOGIC;
sd_dout : out STD_LOGIC_VECTOR(7 downto 0)
);
end bt656gen;
architecture a of bt656gen is
signal state : integer range 0 to 3 :=0;
signal sd_dinTmp : STD_LOGIC_VECTOR(7 downto 0);
signal syn_hTmp: STD_LOGIC;
signal syn_hTmp_tmp1:STD_LOGIC;
signal syn_hTmp_tmp2:STD_LOGIC;
signal syn_fTmp: STD_LOGIC;
signal syn_fTmp_tmp1:STD_LOGIC;
signal syn_fTmp_tmp2:STD_LOGIC;
begin
sd_dout<=sd_dinTmp;
syn_h<=syn_hTmp;
process(clk)
begin
if(clk'event and clk='1') then
sd_dinTmp<=sd_din;
end if;
end process;
process(clk)
begin
if (clk 'event AND clk ='1') then
syn_hTmp_tmp1<=syn_hTmp;
syn_hTmp_tmp2<=syn_hTmp_tmp1;
regenh<=(not syn_hTmp_tmp2)and syn_hTmp;
end if;
end process;
这段程序运行过程中，regenh的输出结果和syn_hTmp到底是什么关系呢？
谢谢~
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