一段ＶＨＤＬ程序，不知道哪里出错了，请大神指点！
--2.状态控制模块（CONTROL_STATUS）LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CONTROL_STATUS IS
PORT(RESET,CLK:IN STD_LOGIC;
STATUS:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
LOAD_EW,LOAD_SN:OUT STD_LOGIC;
DJS_EW,DJS_SN:OUT INTEGER RANGE 0 TO 80);
END CONTROL_STATUS;
ARCHITECTURE ONE OF CONTROL_STATUS IS
SIGNAL T:INTEGER;
BEGIN
PROCESS(CLK)
BEGIN
IF RESET='0' THEN
T<=0;
ELSIF CLK'EVENT AND CLK='1' THEN
LOAD_EW<='0';LOAD_SN<='0';
IF T=0 THEN
STATUS<="000";DJS_EW<=80;LOAD_EW<='1';
ELSIF T=15 THEN
STATUS<="001";DJS_SN<=45;LOAD_SN<='1';
ELSIF T=60 THEN
STATUS<="010";DJS_SN<=5;LOAD_SN<='1';
ELSIF T=65 THEN
STATUS<="011";DJS_SN<=80;LOAD_SN<='1';
ELSIF T=80 THEN
STATUS<="100";DJS_EW<=45;LOAD_EW<='1';
ELSIF T=125 THEN
STATUS<="101";DJS_EW<=5;LOAD_EW<='1';
END IF;
T<=T+1;
IF T=130 THEN
T<=0;
END IF;
END IF;
END PROCESS;
END;
仿真出来应该是这样的： 把T分离出来吧。
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