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This UART chip always produces level active interrupts, and the IIR* only indicates the highest priority interrupt.
* In the case that receive and transmit interrupts happened at the same time, we must clear both interrupt pending to prevent edge-triggered interrupt(output from interrupt controller) from locking up. One way doing it is to disable all the interrupts at the beginning of the ISR and enable at the end.
这段是完整的
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