ps2键盘问题，有的键识别好，有的识别不好 ，各位牛人帮我看看程序啊
module ps2_driver(CLK,ps2_clk_out,RST,data,LED_OUT);inputCLK;
inputRST;
inputps2_clk_out;
inputdata;
output LED_OUT;
reg data_tem;
reg state;
reg LED_OUT_tem;
regclk_r0,clk_r1,clk_r2;
wire neg_ps2_clk;
assign LED_OUT=LED_OUT_tem;
parameteridle =4'b0000,
check_clk =4'b0001,
check_0 =4'b0010,
receive_data0 =4'b0011,
receive_data1 =4'b0100,
receive_data2 =4'b0101,
receive_data3 =4'b0110,
receive_data4 =4'b0111,
receive_data5 =4'b1000,
receive_data6 =4'b1001,
receive_data7 =4'b1010,
receive_p =4'b1011,
receive_1 =4'b1100,
receive_over =4'b1101;
always@(posedge CLK or negedge RST)
begin
if(!RST)
begin
clk_r0<=1'b0;
clk_r1<=1'b0;
clk_r2<=1'b0;
end
else
begin
clk_r0<=ps2_clk_out;
clk_r1<=clk_r0;
clk_r2<=clk_r1;
end
end
assign neg_ps2_clk=(!clk_r1)&clk_r2;
always@(posedge CLK or negedge RST)
begin
if(!RST)
begin
data_tem <=8'h0;
state <=idle;
end
else
if(neg_ps2_clk)
begin
case(state)
idle:
begin
data_tem<=8'h0;
state<=check_clk;
end
check_clk:
begin
state<=check_0;
end
check_0:
begin
if(!data)
begin
state<=receive_data0;
end
else
begin
state<=idle;
end
end
receive_data0:
begin
data_tem<=data;
state<=receive_data1;
end
receive_data1:
begin
data_tem<=data;
state<=receive_data2;
end
receive_data2:
begin
data_tem<=data;
state<=receive_data3;
end
receive_data3:
begin
data_tem<=data;
state<=receive_data4;
end
receive_data4:
begin
data_tem<=data;
state<=receive_data5;
end
receive_data5:
begin
data_tem<=data;
state<=receive_data6;
end
receive_data6:
begin
data_tem<=data;
state<=receive_data7;
end
receive_data7:
begin
data_tem<=data;
state<=receive_p;
end
receive_p:
begin
//if((~^data_tem)==data)
//begin
state<=receive_1;
//end
//else
//begin
//state<=idle;
//end
end
receive_1:
begin
if(data)
begin
state<=receive_over;
end
else
begin
state<=idle;
end
end
receive_over:
begin
state<=idle;
end
default :
begin
data_tem<=8'h0;
state<=idle;
end
endcase
end
end
always@(posedge CLK or negedge RST)
begin
if(!RST)
begin
LED_OUT_tem<=8'b0000_0000;
end
else
begin
if(state==receive_over)
begin
if((data_tem!=8'hf0)&&(data_tem!=8'h00)&&(data_tem!=8'he0))
begin
//LED_OUT_tem<=data_tem;
case (data_tem)
8'h70: LED_OUT_tem<=8'b0000_0001; //0
8'h69: LED_OUT_tem<=8'b0000_0010;
8'h72: LED_OUT_tem<=8'b0000_0011;
8'h7a: LED_OUT_tem<=8'b0000_0111;
8'h6b: LED_OUT_tem<=8'b0000_1000;
8'h73: LED_OUT_tem<=8'b0000_1001;
8'h37: LED_OUT_tem<=8'b0000_1010;
8'h6c: LED_OUT_tem<=8'b0000_1011;
8'h75: LED_OUT_tem<=8'b0000_1100;
8'h7d: LED_OUT_tem<=8'b0000_1101;//9
8'h77: LED_OUT_tem<=8'b0000_1111;//num
8'h4a: LED_OUT_tem<=8'b0001_0000;///
8'h7c: LED_OUT_tem<=8'b0001_0001;//*
8'h7b: LED_OUT_tem<=8'b0001_0010;//-
8'h79: LED_OUT_tem<=8'b0001_0011;//+
8'h5a: LED_OUT_tem<=8'b0001_0100;//enter
8'h75: LED_OUT_tem<=8'b0001_0101;//up
8'h32: LED_OUT_tem<=8'b0001_0110;//down
default:LED_OUT_tem<=8'h00;
endcase
end
end
end
end
endmodule 可以讨论下，有点意思
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