论坛 › FPGA技术交流 › VHDL 不知道错在哪了 我是一个初学者

zhangyasen_8 发表于 2010-12-7 21:46:13

VHDL 不知道错在哪了 我是一个初学者

library ieee;
use ieee.std_logic_1164.all;

entity par_ser is
port(
      clock:   instd_logic;
      parallel_in: instd_logic_vector(7 downto 0);
      serial_out   : outstd_logic
   );
   
end par_ser;

architecture behavior of par_ser is
signal parallel: std_logic_vector(7 downto 0);
begin
parallel(7 downto 0)<=parallel_in(7 downto 0);
process(clock)
begin
   if clock'event and clock='1' then
       serial_out<=parallel(0);
      for I in 0 to 6 loop
         parallel(I)<=parallel(I+1);
      end loop;
   end if;   
end process;
end behavior;

zhangyasen_8 发表于 2010-12-7 21:47:27

编译的时候说是
Error (10031): Net "parallel" at par_ser.vhd(22) is already driven by input port "parallel_in", and cannot be driven by another signal
Error (10032): "parallel_in" was declared at par_ser.vhd(7)
Error (10031): Net "parallel" at par_ser.vhd(22) is already driven by input port "parallel_in", and cannot be driven by another signal
Error (10032): "parallel_in" was declared at par_ser.vhd(7)
Error (10031): Net "parallel" at par_ser.vhd(22) is already driven by input port "parallel_in", and cannot be driven by another signal
Error (10032): "parallel_in" was declared at par_ser.vhd(7)
Error (10031): Net "parallel" at par_ser.vhd(22) is already driven by input port "parallel_in", and cannot be driven by another signal
Error (10032): "parallel_in" was declared at par_ser.vhd(7)
Error (10031): Net "parallel" at par_ser.vhd(22) is already driven by input port "parallel_in", and cannot be driven by another signal
Error (10032): "parallel_in" was declared at par_ser.vhd(7)
Error (10031): Net "parallel" at par_ser.vhd(22) is already driven by input port "parallel_in", and cannot be driven by another signal
Error (10032): "parallel_in" was declared at par_ser.vhd(7)
Error (10031): Net "parallel" at par_ser.vhd(22) is already driven by input port "parallel_in", and cannot be driven by another signal
Error (10032): "parallel_in" was declared at par_ser.vhd(7)

zhouliang 发表于 2010-12-8 09:09:34

解决方法（官方）：

Check the Verilog HDL module or VHDL entity to locate conflicting assignments to the same signal. Remove all but one of the assignments
我的理解是：你的parallel在16行已经赋值了，22行又赋值，这两个是同时进行的，所以出错了

zhouliang 发表于 2010-12-8 09:09:48

解决方法（官方）：

Check the Verilog HDL module or VHDL entity to locate conflicting assignments to the same signal. Remove all but one of the assignments
我的理解是：你的parallel在16行已经赋值了，22行又赋值，这两个是同时进行的，所以出错了

zhouliang 发表于 2010-12-8 10:43:15

你试着把 ‘parallel(7 downto 0)<=parallel_in(7 downto 0);’这句放到process begin后面，看看行不行

zhangyasen_8 发表于 2010-12-8 11:30:50

似乎也不行

zhouliang 发表于 2010-12-8 11:34:10

错误提示是什么

zhangyasen_8 发表于 2010-12-8 11:35:46

Error (10818): Can't infer register for "parallel" at par_ser.vhd(21) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "parallel" at par_ser.vhd(21) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "parallel" at par_ser.vhd(21) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "parallel" at par_ser.vhd(21) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "parallel" at par_ser.vhd(21) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "parallel" at par_ser.vhd(21) because it does not hold its value outside the clock edge
Error (10818): Can't infer register for "parallel" at par_ser.vhd(21) because it does not hold its value outside the clock edge
Error (10822): HDL error at par_ser.vhd(21): couldn't implement registers for assignments on this clock edge

zhangyasen_8 发表于 2010-12-8 12:26:16

好了 把parallel(7 downto 0)<=parallel_in(7 downto 0);放到process里面 在给他加个使能信号就OK了
很谢谢你啊

zhouliang 发表于 2010-12-8 15:36:37

加使能信号，呵呵，又学了一课

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