跪求大牛释疑 Reduced register BCD[31] with stuck data_in port to stuck value GND
小弟初学FPGA，写个程序但仿真没有结果输出，跪求高人赐教，万分感激！仿真中发现程序中BIN_INPUT <= to_bitvector(BIN);没有被执行，或者说BIN_INPUT 始终为零，很是不解，同时发现发现编译中出一些类似Warning : Reduced register "BCD" with stuck data_in port to stuck value GND的警告，不知两者是否有关系，望高人赐教。具体程序如下：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BIN2BCD_Conv_vhdl is
port(
CLK :in std_logic;
EN_Conv :in std_logic;
nRST :in std_logic;
BIN :in std_logic_vector(31 downto 0);
oBCD :out std_logic_vector(31 downto 0)
);
end BIN2BCD_Conv_vhdl;
architecture behav of BIN2BCD_Conv_vhdl is
signal CNT:integer range 0 to 50;
signalENABLE :std_logic;
-- signalBIN_tmp:std_logic_vector(31 downto 0);
signalBCD_I:bit_vector(31 downto 0);
signalBIN_INPUT :bit_vector(31 downto 0);
signalBIN_INPUT_tmp1,BIN_INPUT_tmp2:std_logic_vector(31 downto 0);
signalBIN_INPUT_H,BIN_INPUT_M,BIN_INPUT_S :bit_vector(7 downto 0);
function CORRECT(DECADE:in bit_vector(3 downto 0))return
bit_vector is
variable oData:bit_vector(3 downto 0);
variable oData_tmp,DECADE_tmp:std_logic_vector(3 downto 0);
begin
DECADE_tmp :=to_stdlogicvector(DECADE);
if(DECADE_tmp >= x"5")then
oData_tmp :=(DECADE_tmp+b"0011");
else
oData_tmp :=DECADE_tmp;
end if;
oData :=to_bitvector(oData_tmp);
return oData;
end function CORRECT;
begin
oBCD <=to_stdlogicvector(BCD_I);
process(CLK,nRST)
begin
if(nRST='0')then
BIN_INPUT_tmp1 <= x"0000_0000";
BIN_INPUT_tmp2 <= x"0000_0001";
elsif(CLK'event and CLK='1')then
BIN_INPUT_tmp2 <=BIN_INPUT_tmp1;
BIN_INPUT_tmp1 <= BIN;
end if;
end process;
process(CLK)
begin
if(CLK'event and CLK='0')then
if(BIN_INPUT_tmp1 = BIN_INPUT_tmp2)then
ENABLE <='0';
else
ENABLE <='1';
end if;
end if;
end process;
process(CLK,nRST,BIN,ENABLE)
variableBCD:bit_vector(31 downto 0);
variableBCD_H,BCD_M,BCD_S :bit_vector(7 downto 0);
begin
if(nRST='0')then
-- BCD := x"0000_0000";
BIN_INPUT <= x"0000_0000";
BCD_I <= x"0000_0000";
BCD_H := x"00";
BCD_M := x"00";
BCD_S := x"00";
BIN_INPUT_H <=x"00";
BIN_INPUT_M <= x"00";
BIN_INPUT_S <= x"00";
elsif(CLK'event and CLK='1')then
if(EN_Conv='1')then
if(ENABLE='1')then
CNT <=9;
BCD_H := x"00";
BCD_M := x"00";
BCD_S := x"00";
end if;
if(CNT =9)then
BIN_INPUT_H <=to_bitvector(BIN(23 downto 16));
BIN_INPUT_M <=to_bitvector(BIN(15 downto 8));
BIN_INPUT_S <=to_bitvector(BIN(7 downto 0));
CNT <= CNT -1;
elsif(CNT=0)then
BCD_I(23 downto 0) <= (BCD_H&BCD_M&BCD_S);
else
BCD_H(3 downto 0) := CORRECT(BCD_H(3 downto 0));
BCD_H(7 downto 4) := CORRECT(BCD_H(7 downto 4));
CNT <= CNT -1;--conversion section
BCD_H := (BCD_H srl 1);
BCD_H(0) := BIN_INPUT_H(7);
BIN_INPUT_H <= BIN_INPUT_H srl 1;
BCD_M(3 downto 0) := CORRECT(BCD_M(3 downto 0));
BCD_M(7 downto 4) := CORRECT(BCD_M(7 downto 4));
BCD_M := (BCD_M srl 1);
BCD_M(0) := BIN_INPUT_M(7);
BIN_INPUT_M <= BIN_INPUT_M srl 1;
BCD_S(3 downto 0) := CORRECT(BCD_S(3 downto 0));
BCD_S(7 downto 4) := CORRECT(BCD_S(7 downto 4));
BCD_S := (BCD_S srl 1);
BCD_S(0) := BIN_INPUT_S(7);
BIN_INPUT_S <= BIN_INPUT_S srl 1;
end if;
else
if(ENABLE='1')then
CNT <=33;
BCD :=x"0000_0000";
end if;
if(CNT =33)then
BIN_INPUT <= to_bitvector(BIN);
CNT <= CNT -1;
elsif(CNT = 0)then
BCD_I <= BCD;
else
BCD(3 downto 0) := CORRECT(BCD(3 downto 0));
BCD(7 downto 4) := CORRECT(BCD(7 downto 4));
BCD(11 downto 8) := CORRECT(BCD(11 downto 8));
BCD(15 downto 12) := CORRECT(BCD(15 downto 12));
BCD(19 downto 16) := CORRECT(BCD(19 downto 16));
BCD(23 downto 20) := CORRECT(BCD(23 downto 20));
BCD(27 downto 24) := CORRECT(BCD(27 downto 24));
BCD(31 downto 28) := CORRECT(BCD(31 downto 28));
CNT <= CNT -1;--conversion section
BCD := (BCD srl 1);
BCD(0) := BIN_INPUT(31);
BIN_INPUT <= BIN_INPUT srl 1;
end if;
end if;
end if;
end process;
end behav;
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