VHDL关于单稳触发的程序求助。
程序如下：library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DH_1 IS
PORT (
clk : IN std_logic;
TRIG : OUT std_logic;
END DH_1;
ARCHITECTURE arch OF DH_1 IS
constant N:Integer:=999;
constant RC_N:Integer:=10;
signal RC:Integer range 0 TO 100;
signal TRIG_RC:std_logic;
signal TRIG_ON:std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if counter=N THEN --N=9999
counter<=0;
TRIG_ON<= NOT TRIG_ON;--将clk分频为1ms信号TRIG_ON
else
counter<=counter+1;
end if;
end if;
end process;
PROCESS(clk)
begin
if rising_edge(TRIG_ON)then
RC<=0;
end if;
If RC<10 then
RC<=RC+1;
TRIG_RC<='1';
else
TRIG_RC<='0';
end if;
end process;
process(clk)
begin
TRIG<= TRIG_ON AND TRIG_RC;
end process;
end arch;
程序的意图是想形成一频率及一定宽度的脉冲。首先TRIG_ON由时钟频率而来，同时在TRIG_ON上升沿来临时对信号RC置0后在递加+，当达到所需要宽度时，再将TRIG_RC置低。但是上面的程序无法实现这个功能。请大家帮我找找毛病，谢谢！ 建议：编写测试模块在modelsim环境下仿真，逐个信号进行观察分析，看看问题是卡在哪个地方，然后再解决问题
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