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usb 发表于 2010-6-28 12:01:37

你到底想问什么呀?

usd 发表于 2010-6-28 12:09:02

我觉得最好能有人给出个串并并串的例子，这样就好了，光说个移位寄存器，不明白啊，和楼主一同期待

interig 发表于 2010-6-28 13:43:09

还是要个完整的例子才适合我们这样的入门菜鸟

VVIC 发表于 2010-6-28 13:46:18

顶一个，确实不错

longt 发表于 2010-6-28 14:30:07

都可以采用移位寄存器实现

longt 发表于 2010-6-28 15:28:44

begin 
counter: process(reset,clk,shift_start) 
begin 
  if(reset = '0') then 
   cnt <= (others => '0'); 
  elsif(clk'event and clk = '1') then 
   if(shift_start = '0') then 
    cnt <= cnt + 1; 
   else 
    cnt <= (others => '0'); 
   end if; 
  end if; 
end process counter; 
 
fsm: block 
begin 
  sync: process(reset,clk) 
  begin 
   if(reset= '0') then 
    current_state <= idle; 
   elsif(clk'event and clk = '1') then 
    current_state <= next_state; 
   end if; 
  end process sync; 
 
  comb: process(current_state,cnt,start) 
  begin 
   case current_state is 
    when idle => 
     ready <= '0'; 
     reg_en <= '1'; 
     shift_start <= '1'; 
     data_valid <= '1'; 
     if(start = '0') then 
      reg_en <= '0'; 
      next_state <= recieve; 
     else 
      next_state <= idle; 
     end if; 
    when recieve => 
     reg_en <= '1'; 
     ready <= '1'; 
     data_valid <= '0'; 
     shift_start <= '0'; 
     next_state <= shift; 
    when shift => 
     reg_en <= '1'; 
     ready <= '1'; 
     data_valid <= '0'; 
     if(cnt = 8) then 
      shift_start <= '1'; 
      next_state <= finish; 
     else 
      shift_start <= '0';       
      next_state <= shift; 
     end if; 
    when finish => 
     reg_en <= '1'; 
     ready <= '0'; 
     data_valid <= '1'; 
     shift_start <= '1'; 
     next_state <= idle; 
    when others => 
     next_state <= idle; 
   end case; 
  end process comb; 
 
end block fsm; 
 
data_channel: process(reset,clk) 
begin 
  if(reset = '0') then 
   reg <= (others => '0'); 
   q   <= '0'; 
  elsif(clk'event and clk = '1') then 
   if(reg_en = '0') then 
    reg <= data_in; 
   elsif(shift_start = '0') then 
    q <= reg(7); 
    for i in 7 downto 1 loop    --shift register 
     reg(i) <= reg(i - 1); 
    end loop; 
    reg(0) <= '0'; 
   else   
    q <= '0'; 
   end if; 
  end if; 
end process data_channel; 
 
end Behavioral; 
 
并串转换,,整个代码已经通过了后仿真，而且思路还是比较清楚的，可靠性和稳定性方面也应该没有问题滴，呵呵。不过说老实话，里面有些信号是确实可以去掉的，不过后来就懒得改了。如果谁想要实际的工程中用的话可以改一下。

longtime 发表于 2010-6-28 16:24:20

随便一本教硬件语言的都有吧

UFP 发表于 2010-6-28 17:07:31

移位寄存器和状态机都可以，不过移位寄存器要简单的多

usb 发表于 2010-6-28 17:39:53

就是状态机有一点麻烦，不过有时候却有好处

HDL 发表于 2010-6-28 17:45:10

很简单的，就用移位寄存器搞定

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